Power amplifiers using RF power transistors suffer from a reduction in gain with increasing frequency due to parasitic effects in the transistors. One of the most limiting parasitic effects in large power transistors used at high frequencies is the so called “effective common-lead inductance”, i.e. the magnetic coupling between the input and output loops of the transistor, causing inductive feedback. A number of techniques can be used to reduce that coupling. One can e.g. use substrate vias, a conductive substrate, or a large number of bond wires connected to ground. A differential amplifier is another option, which also suppresses even harmonics, and has doubled input and output impedance levels.
Such power amplifiers are commonly built from two discrete transistors, in separate packages, or on separate dies in the same package, or one the same die but located in two separate groups.
FIG. 1 is a schematic cross-sectional view of an embodiment of a known differential transistor pair.
Two discrete LDMOS RF power transistors 1, 2 are located on a common package ground plane 3.
In a manner known per se, each transistor 1, 2 comprises in a substrate 4 and 5, respectively, a plurality of transistor cells C1, C2, each comprising a source region, a gate region, and a drain region.
Each such cell C1, C2 comprises a source region S, a gate region G and a drain region D as illustrated more in detail above the transistor 1 in FIG. 1. In a manner known per se, the source region S is connected to a substrate contact SC via a metal clamp C.
In each transistor 1, 2, all gate regions are coupled in parallel and connected to a common gate terminal (not illustrated). Moreover, all drain regions are coupled in parallel and connected to a common drain terminal (not illustrated) in each transistor 1, 2.
The source regions of the transistors 1, 2 are all interconnected via the heavily doped substrates 4, 5 and the ground plane 3.
In operation, RF current will flow from the gate region G and the drain region D of transistor 1 through the channel of transistor 1, through the source region S of transistor 1 and into the metal clamp C of transistor 1, through the substrate contact SC of transistor 1, through the substrate 4 of transistor 1, through the ground plane 3 and into the substrate 5 of transistor 2, through the substrate contact (not shown) of transistor 2, through the metal clamp (not shown) of transistor 2 and into the source region (not shown) of transistor 2, through the channel (not shown) of transistor 2 and into the gate region (not shown) and the drain region (not shown) of transistor 2 as indicated by line 6 in FIG. 1.
Since the effective impedance between the source regions of the transistors 1 and 2 is non-zero at RF and common to both input and output loops of the transistors, the gain will be reduced due to feedback in the known differential transistor pair.